While mass data backup storage in data processing systems has so far relied on magnetic disk drives, the relatively high failure rate of these devices, their fragility, bulkiness and high power consumption (all the results of the devices' heavy dependence upon high precision moving mechanical parts) have led the industry to seek replacements therefor.
One of the heavily pursued candidates is semiconductor memory. While several types of semiconductor memories exist, not all of them can feasibly be used for mass storage of data. For example, random access memory (RAM), being a volatile memory requiring constant supply of electrical power to maintain its memory, is more suitable to be used as temporary working storage and not for mass data backup. And while read only memory (ROM) programmable read only memory (PROM) and ultra-violet programmable read only memory (UVPROM) are non-volatile, the impossibility, or difficulties, in altering their contents have rendered these memories unsuitable for backup mass data storage.
Recently, an interest has been developed in using electrically erasable programmable read only memory (EEPROM) and Flash EEPROM for mass data storage.
EEPROM and Flash EEPROM, and the implementation thereof to serve as mass storage and replace magnetic disk drives, are disclosed in pending U.S. Pat. No. 337,566 of Harari et al., filed Apr. 13, 1989, and co-pending U.S. Pat. No. 422,949 of Gross et al., filed Oct. 17, 1989, both of which have the same assignee as the present application.
Essentially, EEPROM or Flash EEPROM are field effect transistors each with an additional polysilicon region generally referred to as the floating gate. Data is “memorized” through confinement of predefined amounts of electric charge in this floating gate.
The electric charge are transferred to the floating gate from the substrate through a dielectric region. They affect the conductivity of the source-drain channel and the threshold voltage of the field effect transistor. Physically, the differences in threshold voltages and the differences in the source-drain currents, due to the confinement of different amounts of electric charge in the floating gates, can then be used to define different logic states (e.g. “0”, “1”, . . . ). Demarcation threshold voltage levels may be used to demarcate between the different logic states. For example, a “0” or “1” state would respectively have a programmed threshold voltage level less than or greater than the demarcation threshold voltage level between these two states.
Thus each memory cell is capable of supporting a range of threshold voltage levels within a “threshold window” spanned by a maximum and minimum programmable threshold voltage level. Schematically, the threshold window may be partitioned into threshold voltage domains, each representing a memory state. Each domain may be defined by a pair of demarcation threshold voltage levels. In practice, a given memory state is represented by programming a threshold voltage level well within its corresponding domain, preferably located in the middle, with equal margins on either side of the pair of demarcation levels.
Traditionally, EEPROM and Flash EEPROM are used in applications where semi-permanent storage of data or program is required but with limited reprogramming. But as EEPROM and Flash EEPROM are now intended to replace magnetic disks, a new requirement surfaces—the requirement to maintain reliability and availability with increased program/erase cycles.
As with most devices, EEPROM and Flash EEPROM are susceptible to defects and failures. One consequence is the occurrence of soft errors caused by the gradual shifting of the threshold level of the memory states. The shifting of the threshold level is partly due to ambient conditions and mostly due to stress from normal operations of the memory device such as erase, program or read. As discussed earlier, a cell's threshold level is typically programmed with a margin from the demarcation levels. When the threshold level is shifted from its programmed level, the reliability of reading the intended memory state may be compromised. These soft errors, in their initial stages, are not severe enough to be readily detected during normal operations of the memory device. However, if the shifting is allowed to continue beyond the error margin allowed by the normal read circuit, the soft errors will eventually develop into hard errors and produce read errors. In that event, the hard errors may be corrected by some sort of error correction scheme such as an error correction code (ECC), and the cells in question may be mapped out. However, if too many hard errors had developed at the same time, the errors may be uncorrectable because they overload the capacity of the error correction scheme used. Thus, the capacity of the memory device may gradually be decimated, and worse still, possible uncorrectable errors can render the memory device unreliable.
The above identified failures are unfamiliar to engineers and scientists working on other semiconductor memories. For example, whereas DRAM may also suffer from failures due to charge leakage, such leakage is predominantly the result of bombardment by alpha particles. Thus, DRAM failures are instantaneous, unpredictable, random and independent of the program/erase circles. On the other hand, EEPROM failures are generally gradual, predictable and depend upon the number of times a memory is erased and programmed. Moreover, whereas DRAM failures are isolated, EEPROM failures are aggregative, as a group of cells may be subjected to repeated memory operations. When failures occur in aggregate, they may overload known error correction schemes.
The different characteristics of the failures between DRAM and EEPROM thus demand prevention techniques that are completely different from those available to DRAM designers.
Co-pending U.S. Pat. No. 337,566 of Harari et al. discloses a scheme of detecting and handling errors “on-the-fly” by verifying each memory operation, such as read, program or erase, after its has been performed. A verification failure indicates a defective cell, and the address of a defective cell is re-mapped the address of a good one. Similarly co-pending U.S. Pat. No. 422,949 of Gross et al. discloses a scheme of detecting and handling errors “on-the-fly.”
These error detection schemes are based on detecting errors cell-by-cell, by sensing abnormal read, program or erase operating conditions of the memory devices. However, they are not effective in preventing soft errors which may later deteriorate into catastrophic errors. For example, a small voltage drop caused by a soft error may escape detection by the schemes disclosed in these co-pending applications because it is still within the margin of error allowed by the read, program or erase operations. But a group of cells may continue to deteriorate until they cross the margin of errors together. At that point, remedies may be unavailable.
What is needed is an error correction scheme that is capable of preventing and correcting mass data deteriorations.
Accordingly, it is an object of the invention to provide a Flash EEPROM or EEPROM device with improved reliability.
It is another object of the invention to provide a Flash EEPROM or EEPROM device capable of detecting and correcting potential errors during the lifetime of the device.
It is yet another object of the invention to provide a Flash EEPROM or EEPROM device capable of recovering data from read errors which may not be correctable by available error correction schemes.